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ELECTRONICS MECHANIC - CITS



           blocks. The first 128 bytes of internal data memory are both directly and indirectly addressable. The upper 128
           bytes of data memory (from 0x80 to 0xFF) can be addressed only indirectly.
           Since internal data memory is used for CALL stack also and there are only 256 bytes splinted over a few different
           memory areas, fine utilizing of this memory is crucial for fast and compact code. See types efficiency also.
           Memory block in the range of 20h to 2Fh is bit-addressable, which means that each bit being there has its own
           address from 0 to 7Fh. Since there are 16 such registers, this block contains a total of 128 bits with separate
           addresses (Bit 0 of byte 20h has the bit address 0, and bit 7 of byte 2Fh has the bit address 7Fh).
           Three memory type specifiers can be used to refer to the internal data memory: data, idata, and bdata.
           External Data Memory
           Access  to  external  memory  is  slower  than  access  to  internal  data  memory. There  may  be  up  to  64K  Bytes
           of external data memory. Several 8051 devices provide on-chip XRAM space that is accessed with the same
           instructions as the traditional external data space. This XRAM space is typically enabled via proper setting of SFR
           register and overlaps the external memory space. The setting of that register must be manually done in code,
           before any access to external memory or XRAM space is made.

           The micro-PRO for 8051 has two memory type specifiers that refers to external memory space: xdata and pdata.

            8051 Microcontroller Hardware


           The 8051 architecture consists of these specific features:
           Eight-bit CPU with:
           Register A (the Accumulator)
           Register B
           Instruction set
           Sixteen-bit program counter (PC) and data pointer (DPTR)
           Eight-bit program status (PSW)

           Eight-bit stack pointer (SP)
           Internal ROM or EPROM (8751) of 0(8031) to 4K (8051)
           Internal RAM of 128 bytes:
           Four register banks, each containing eight registers

           Sixteen bits, which may be addressed at the bit level:
           128 addressable bits
           Eighty bytes of general-purpose data memory
           Thirty-two input/output pins arranged as four 8-bit ports: P0-P3
           Two 16-bit timer/counters: T0 and T1

           Full duplex serial data receiver/transmitter: SBUF
           Control registers:
           TCON
           TMOD
           SCON

           PCON
           IP
           IE





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                                    CITS : E & H - Electronics Mechanic - Lesson 34 - 42
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